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10 w, gan power amplifier, 2.7 ghz to 3.8 ghz data sheet hmc1114 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features high saturated output power (p sat ): 41.5 dbm typical high small signal gain: 35 db typical high power gain for saturated output power: 25.5 db typical bandwidth: 2.7 ghz to 3.8 ghz high power added efficiency (pae): 54% typical high output ip3: 44 dbm typical supply voltage: v dd = 28 v at 150 ma 32-lead, 5 mm 5 mm lfcsp_cav package applications extended battery operation for public mobile radios power amplifier stage for wireless infrastructure test and measurement equipment commercial and military radars general-purpose transmitter amplification functional block diagram 17 1 3 4 2 9 gnd gnd gnd rfin 5 6 rfin gnd 7 gnd 8 gnd gnd 18 gnd 19 gnd 20 rfout 21 rfout 22 gnd 23 gnd 24 gnd gnd 1 2 gnd 1 1 gnd 1 0 v gg1 1 3 v gg2 1 4 gnd 1 5 gnd 1 6 gnd 2 5 gnd 2 6 v dd2 2 7 v dd2 2 8 gnd 2 9 gnd 3 0 v dd1 3 1 gnd 3 2 gnd hmc1114 13530-001 package base figure 1. general description the hmc1114 is a gallium nitride (gan), broadband power amplifier, delivering 10 w with more than 50% power added efficiency (pae) across a bandwidth of 2.7 ghz to 3.8 ghz. the hmc1114 provides 0.5 db gain flatness. the hmc1114 is ideal for pulsed or continuous wave (cw) applications such as wireless infrastructure, radar, public mobile radio, and general-purpose amplification. the hmc1114 is housed in a compact lfcsp_cav package.
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hmc1114 data sheet rev. 0 | page 2 of 15 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical spe cifications ............................................................... 3 total supply current by v dd ....................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 interface schematics .....................................................................5 typical performance characteristics ..............................................6 theory of operation ...................................................................... 12 applications information .............................................................. 13 recommended bias sequence .................................................. 13 typical application circuit ....................................................... 13 evaluation printed circuit board (pcb) ..................................... 14 bill of materials ........................................................................... 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 revision hi story 9/2016 revision 0 : initial version
data sheet hmc1114 rev. 0 | page 3 of 15 specifications electrical specifica tions t a = 25c, v dd = 28 v, i d q = 15 0 ma , frequency range = 2 .7 ghz to 3 .2 ghz , unless otherwise noted . table 1 . parameter symbol min typ max unit test conditions/comments frequency range 2 . 7 3 . 2 ghz gain small signal gain 32 35 db gain flatness 0. 5 db power gain for 4 db compression 29 db power gain for saturated output power 25.5 db measurement taken at p in = 16 dbm return loss input 1 4 db output 1 1 db power output power for 4 db compression p 4 db 3 9 dbm saturated output power p sat 41.5 dbm measurement taken at p in = 16 dbm power added efficiency pae 54 % output third - order intercept ip3 44 measurement taken at p out / tone = 30 dbm target quie scent current i d q 150 ma adjust the gate control voltage ( v gg1 , v gg2 ) between ? 8 v and 0 v to achieve an i d q = 15 0 ma typical t a = 25c, v dd = 28 v, i d q = 15 0 ma, frequency range = 3 .2 ghz to 3.8 ghz , unless otherwise noted . table 2 . parameter symbol min typ max unit test conditions/comments frequenc y range 3.2 3.8 ghz gain small signal gain 29 32 db gain flatness 1 db power gain for 4 db compression 28 db power gain for saturated output power 25 db measurement taken at p in = 16 dbm return loss input 25 db output 9 db power output power for 4 db compression p4db 40 dbm saturated output power p sat 40.5 dbm measurement taken at p in = 16 dbm power added efficiency pae 53 % output third - order intercept ip3 44 measurement taken at p out / tone = 30 dbm target quie scent current i dq 150 ma adjust the gate control voltage ( v gg1 , v gg2 ) between ?8 v and 0 v to achieve an i dq = 150 ma typical total supply current by v dd table 3 . parameter symbol min typ max unit test conditions/comments supply c urrent i d q adjust v gg1 , v gg2 to achieve an i d q = 15 0 ma typical v dd = 25 v 150 ma v dd = 28 v 150 ma v dd = 32 v 150 ma
hmc1114 data sheet rev. 0 | page 4 of 15 absolute maximum ratings table 4. parameter rating drain bias voltage (v dd1 , v dd2 ) 35 v dc gate bias voltage (v gg1 , v gg2 ) ?8 v to 0 v dc rf input power (rfin) 30 dbm maximum forward gate current 4 ma continuous power dissipation, p diss (t a = 85c, derate 227 mw/c above 120c) 24 w thermal resistance, junction to back of paddle 4.4c/w channel temperature 225c maximum peak reflow temperature (msl3) 1 260c storage temperature range ?40c to +125c operating temperature range ?40c to +85c esd sensitivity (human body model) class 1a, passed 250 v 1 see the ordering guide section. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
data sheet hmc1114 rev. 0 | page 5 of 15 pin configuration and fu nction descriptions 17 1 3 4 2 9 gnd gnd gnd rfin 5 6 rfin gnd 7 gnd 8 gnd gnd 18 gnd 19 gnd 20 rfout 21 rfout 22 gnd 23 gnd 24 gnd gnd 1 2 gnd 1 1 gnd 1 0 v gg1 1 3 v gg2 1 4 gnd 1 5 gnd 1 6 gnd 2 5 gnd 2 6 v dd2 2 7 v dd2 2 8 gnd 2 9 gnd 3 0 v dd1 3 1 gnd 3 2 gnd hmc1114 top view (not to scale) 13530-002 notes 1. exposed pad. exposed pad must be connected to rf/dc ground. figure 2. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 to 3, 6 to 9, 11, 12, 14 to 19, 22 to 25, 28, 29, 31, 32 gnd ground. these pins and the package bottom (epa d) must be connected to rf/dc ground. see figure 3 for the gnd interface schematic. 4, 5 rfin rf input. these pins are dc-coupled and matched to 50 . see figure 4 for the rfin interface schematic. 10, 13 v gg1 , v gg2 gate control voltage pins. external bypass capa citors of 1 f and 10 f are required. see figure 5 for the v gg1 and v gg2 interface schematic. 20, 21 rfout rf output. these pins are ac-coupled and matched to 50 . see figure 6 for the rfout interface schematic. 26, 27, 30 v dd1 , v dd2 drain bias pins for the amplifier. external bypass capacitors of 100 pf, 1 f, and 10 f are required. see figure 7 for the v dd1 and v dd2 interface schematic. epad exposed pad. the exposed pad must be connected to rf/dc ground. interface schematics gnd 13530-003 figure 3. gnd interface rfin 13530-004 figure 4. rfin interface v gg1 , v gg2 13530-005 figure 5. v gg1 and v gg2 interface rfout 13530-006 figure 6. rfout interface v dd1 , v dd2 13530-007 figure 7. v dd1 and v dd2 interface
hmc1114 data sheet rev. 0 | page 6 of 15 typical performance characteristics 40 ?40 ?20 ?30 ?10 0 10 20 30 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 response (db) frequency (ghz) s22 s21 s11 13530-008 figure 8. response (gain and return loss) vs. frequency 0 ?40 ?30 ?35 ?25 ?20 ?15 ?10 ?5 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 input return loss (db) frequency (ghz) +85c +25c ?40c 13530-009 figure 9. input return loss vs. frequency at various temperatures 40 20 24 28 32 36 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 gain (db) frequency (ghz) 32v 28v 25v 20v 13530-010 figure 10. gain vs. frequency at various supply voltages 40 20 24 28 32 36 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 gain (db) frequency (ghz) +85c +25c ?40c 13530-011 figure 11. gain vs. frequency at various temperatures 0 ?20 ?15 ?10 ?5 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 output return loss (db) frequency (ghz) +85c +25c ?40c 13530-012 figure 12. output return loss vs. frequency at various temperatures 40 20 24 28 32 36 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 gain (db) frequency (ghz) 300ma 225ma 150ma 100ma 13530-013 figure 13. gain vs. frequenc y at various supply currents
data sheet hmc1114 rev. 0 | page 7 of 15 44 30 32 34 38 42 36 40 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 p out (dbm) frequency (ghz) p1db p4db p sat at p in = 16dbm 13530-014 figure 14. output power (p out ) vs. frequency, measurement taken at p in = 16 dbm 44 30 32 34 38 42 36 40 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 p4db (dbm) frequency (ghz) 32v 28v 25v 20v 13530-015 figure 15. output power for 4 db compression (p4db) vs. frequency at various supply voltages 44 30 32 34 38 42 36 40 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 p sat (dbm) frequency (ghz) 32v 28v 25v 20v 13530-016 figure 16. saturated output power (p sat ) vs. frequency at various supply voltages, measurement taken at p in = 16 dbm 44 30 32 34 38 42 36 40 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 p4db (dbm) frequency (ghz) +85c +25c ?40c 13530-017 figure 17. output power for 4 db compression (p4db) vs. frequency at various temperatures 44 30 32 34 38 42 36 40 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 p sat (dbm) frequency (ghz) +85c +25c ?40c 13530-018 figure 18. saturated output power (p sat ) vs. frequency at various temperatures, measurement taken at p in = 16 dbm 44 30 32 34 38 42 36 40 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 p4db (dbm) frequency (ghz) 300ma 225ma 150ma 100ma 13530-019 figure 19. output power for 4 db compression (p4db) vs. frequency at various supply currents
hmc1114 data sheet rev. 0 | page 8 of 15 44 30 32 34 38 42 36 40 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 p sat (dbm) frequency (ghz) 300ma 225ma 150ma 100ma 13530-020 figure 20. saturated output power (p sat ) vs. frequency at various supply currents, measurement taken at p in = 16 dbm 50 34 38 36 40 44 48 42 46 2.6 2.8 3.0 3.2 3.4 3.6 3.8 output ip3 (dbm) frequency (ghz) +85c +25c ?40c 13530-021 figure 21. output third-order intercept (ip3) vs. frequency at various temperatures, p out /tone = 30 dbm 35 15 19 23 29 33 27 17 21 25 31 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 power gain (db) frequency (ghz) p1db p4db p sat at p in = 16dbm 13530-022 figure 22. power gain vs. frequency 2.6 2.8 3.0 3.2 3.4 3.6 3.8 50 34 38 36 40 44 48 42 46 output ip3 (dbm) frequency (ghz) 32v 28v 25v 20v 13530-023 figure 23. output third-order intercept (ip3) vs. frequency at various supply voltages, p out /tone = 30 dbm 2.62.83.03.23.43.63.8 50 34 38 36 40 44 48 42 46 output ip3 (dbm) frequency (ghz) 300ma 225ma 150ma 100ma 13530-024 figure 24. output third-order intercept (ip3) vs. frequency at various supply currents, p out /tone = 30 dbm 50 10 20 35 45 30 15 25 40 15 17 19 21 23 27 31 25 29 33 35 output im3 (dbc) p out /tone (dbm) 3.8ghz 3.25ghz 2.7ghz 13530-025 figure 25. output third-order intermodulation (im3) vs. p out /tone at v dd = 20 v
data sheet hmc1114 rev. 0 | page 9 of 15 50 10 20 35 45 30 15 25 40 15 17 19 21 23 27 31 25 29 33 35 output im3 (dbc) p out /tone (dbm) 3.8ghz 3.25ghz 2.7ghz 13530-028 figure 26. output third-orde r intermodulation (im3) vs. p out /tone at v dd = 25 v 50 10 20 35 45 30 15 25 40 15 17 19 21 23 27 31 25 29 33 35 output im3 (dbc) p out /tone (dbm) 3.8ghz 3.25ghz 2.7ghz 13530-026 figure 27. output third-order intermodulation (im3) vs. p out /tone at v dd = 28 v 60 10 30 50 20 40 1500 0 150 450 1050 1350 750 300 600 900 1200 ?4 0 4 8 12 16 20 24 p out (dbm), gain (db), pae (%) i dd (ma) input power (dbm) p out gain pae i dd 13530-027 figure 28. output power (p out ), gain, power added e fficiency (pae), and supply current (i dd ) vs. input power at 2.7 ghz 50 10 20 35 45 30 15 25 40 15 17 19 21 23 27 31 25 29 33 35 output im3 (dbc) p out /tone (dbm) 3.8ghz 3.25ghz 2.7ghz 13530-029 figure 29. output third-orde r intermodulation (im3) vs. p out /tone at v dd = 32 v 60 10 30 50 20 40 1000 0 100 300 700 900 500 200 400 600 800 ?4 0 4 8 12 16 20 24 p out (dbm), gain (db), pae (%) i dd (ma) input power (dbm) p out gain pae i dd 13530-030 figure 30. output power (p out ), gain, power added e fficiency (pae), and supply current (i dd ) vs. input power at 3.2 ghz 60 10 30 50 20 40 1000 0 100 300 700 900 500 200 400 600 800 ?4 0 4 8 12162024 p out (dbm), gain (db), pae (%) i dd (ma) input power (dbm) p out gain pae i dd 13530-031 figure 31. output power (p out ), gain, power added e fficiency (pae), and supply current (i dd ) vs. input power at 3.8 ghz
hmc1114 data sheet rev. 0 | page 10 of 15 0 ?70 ?60 ?40 ?20 ?50 ?30 ?10 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 reverse isolation (db) frequency (ghz) +85c +25c ?40c 13530-032 figure 32. reverse isolation vs. frequency at various temperatures 45 20 30 40 25 35 100 150 200 250 300 gain (db), p4db (dbm), p sat (dbm) i dd (ma) p1db p4db p sat at p in = 16dbm 13530-033 figure 33. gain, output power for 4 db compression (p4db), and saturated output power (p sat ) vs. supply current (i dd ) 80 10 20 40 60 30 50 70 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 pae (%) frequency (ghz) +85c +25c ?40c 13530-034 figure 34. power added efficiency (pae) vs. frequency at various temperatures, p in = 16 dbm 45 20 30 40 25 35 24 25 26 27 28 gain (db), p4db (dbm), p sat (dbm) v dd (v) p1db p4db p sat at p in = 16dbm 13530-035 figure 35. gain, p4db, and p sat vs. supply voltage (v dd ) at 3.2 ghz 20 0 6 14 18 12 2 8 4 10 16 0 5 10 15 20 25 power dissipation (w) input power (dbm) 3.8ghz 3.25ghz 2.7ghz 13530-036 figure 36. power dissipation vs. input power at 85c 40 0 5 10 20 30 15 25 35 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 second harmonic (dbc) frequency (ghz) +85c +25c ?40c 13530-037 figure 37. second harmonic vs. frequency at various temperatures, p out = 30 dbm
data sheet hmc1114 rev. 0 | page 11 of 15 40 0 5 10 20 30 15 25 35 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 second harmonic (dbc) frequency (ghz) 32v 28v 25v 20v 13530-038 figure 38. second harmonic vs. frequency at various supply voltages, p out = 30 dbm 50 45 40 0 5 10 20 30 15 25 35 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 second harmonic (dbc) frequency (ghz) 20dbm 25dbm 30dbm 35dbm 40dbm 13530-039 figure 39. second harmonic vs. frequency at various output powers
hmc1114 data sheet rev. 0 | page 12 of 15 theory of operation the hmc1114 is a 10 w, gallium nitride (gan), power amplifier that consists of two gain stages in series, and the basic block diagram for the amplifier is shown in figure 40. v dd1 v gg1 rfin rfout v gg2 v dd2 v dd2 13530-140 figure 40. basic block diagram the recommended dc bias conditions put the device in deep class ab operation, resulting in high p sat (41.5 dbm typical) at improved levels of pae (54% typical). the voltage applied to the v gg1 and v gg2 pads sets the gate bias of the field effect transistors (fets), providing control of the drain current. for this reason, the application of a bias voltage to the v gg1 and v gg2 pads is required and not optional. the hmc1114 has single-ended input and output ports whose impedances are nominally equal to 50 over the 2.7 ghz to 3.8 ghz frequency range. consequently, it can directly insert into a 50 system with no required impedance matching circuitry, which also means that multiple hmc1114 amplifiers can be cascaded back to back without the need for external matching circuitry. the input and output impedances are sufficiently stable vs. variations in temperature and supply voltage that no impedance matching compensation is required. note that it is critical to supply very low inductance ground connections to the gnd pins and the package base exposed pad to ensure stable operation. to achieve optimal performance from the hmc1114 and prevent damage to the device, do not exceed the absolute maximum ratings.
data sheet hmc1114 rev. 0 | page 13 of 15 applications information figure 41 shows the basic connections for operating the hmc1114 . the rfin port is dc-coupled. an appropriate valued external dc block capacitor is required at rfin port. the rfout port has on-chip dc block capacitors that eliminate the need for external ac coupling capacitors. recommended bias sequence during power-up the recommended bias sequence during power-up is the following: 1. connect to ground. 2. set v gg1 and v gg2 to ?8 v. 3. set v dd1 and v dd2 to 28 v. 4. increase v gg1 and v gg2 to achieve a typical i dq = 150 ma. 5. apply the rf signal. during power-down the recommended bias sequence during power-down is the following: 1. tur n of f t he rf sig na l. 2. decrease v gg1 to ?8 v to achieve a typical i dq = 0 ma. 3. decrease v dd1 and v dd2 to 0 v. 4. increase v gg1 to 0 v. unless otherwise noted, all measurements and data shown were taken using the typical application circuit (see figure 41) on the evaluation board (see figure 42) and biased per the conditions in the recommended bias sequence section. the v dd1 and two v dd2 pins are connected together. similarly, the v gg1 and v gg2 pins are also connected together. the bias conditions shown in the recommended bias sequence section are the operating points recommended to optimize the overall performance. operation using other bias conditions may provide performance that differs from what is in table 1 and table 2. increasing the v dd1 and v dd2 levels typically increase gain and p sat at the expense of power consumption. this behavior is seen in the typical performance characteristics section. for applications where the p sat requirement is not stringent, reduce the v dd1 and the v dd2 of the hmc1114 to improve power consumption. to obtain the best performance while not damaging the device, follow the recommended biasing sequence outlined in the recommended bias sequence section. typical application circuit 17 1 3 4 2 9 5 6 7 8 18 19 20 21 22 23 24 12 11 10 13 14 15 16 25 26 27 28 29 30 31 32 c2 1000pf v dd1 , v dd2 v gg1 , v gg2 rfin rfout c3 1f c8 10f c6 10f c4 1f c9 10f c5 1f c10 10f c7 10f c1 1000pf 13530-040 hmc1114 figure 41. typical application circuit
hmc1114 data sheet rev. 0 | page 14 of 15 evaluation printed circuit board (pcb) the evl1hmc1114lp5d (600-01209-00) evaluation pcb is shown in figure 42. bill of materials use rf circuit design techniques for the circuit board used in the application. provide 50 impedance for the signal lines and directly connect the package ground leads and exposed paddle to the ground plane, similar to that shown in figure 42. use a sufficient number of via holes to connect the top and bottom ground planes. the evaluation pcb shown in figure 42 is available from analog devices, inc., upon request. j3 1 gnd gnd vdd1/vdd2 c7 c8 c6 c1 c3 c2 u1 c4 c9 c5 c10 jp1 rfin j 1 j2 rfout vgg1/vgg2 13530-041 figure 42. evaluation printed circuit board (pcb) table 6. bill of materials for evaluation pcb evl1hmc1114lp5d (600-01209-00) item description j1, j2 sma connectors j3 dc pins jp1 preform jumper c1, c2 1000 pf capacitors, 0603 package c3 to c6 1 f capacitors, 0603 package c7 to c10 10 f capacitors, 1210 package u1 hmc1114lp5de pcb 600-01209-00 evaluation pcb; circuit board material: rogers 4350 or arlon 25fr
data sheet hmc1114 rev. 0 | page 15 of 15 outline dimensions 03-30-2016-a 1 0.50 bsc bottom view top view side view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r seating plane coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 1.53 1.35 1.15 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.55 0.50 0.35 0.50 min 3.15 3.00 sq 2.85 pkg-004844 3.50 ref 6 bsc 4.81 ref sq figure 43. 32-lead lead frame chip scale package, premolded cavity [lfcsp_cav] 5 mm 5 mm body and 1.34 mm package height (cg-32-1) dimensions shown in millimeters ordering guide model 1, 2, temperature msl rating 3 description 4 package option package marking 5 hmc1114lp5de ?40c to +85c msl3 32-lead lead frame chip scale package, premolded cavity [lfcsp_cav] cg-32-1 xxxx h1114 HMC1114LP5DETR ?40c to +85c msl3 32-lead lead frame chip scale package, premolded cavity [lfcsp_cav] cg-32-1 xxxx h1114 evl1hmc1114lp5d evaluation board 1 the hmc1114lp5de and the HMC1114LP5DETR are lfcsp premolded copper alloy le ad frame and rohs compliant parts. 2 when ordering the evaluati on board only, reference the evl1hmc1114lp5d model number. 3 see the absolute maximum ratings se ction for additional information. 4 the lead finish of the hmc1114lp5de and hmc 1114lp5detr are nickel pa lladium gold (nipdau). 5 the hmc1114lp5de and HMC1114LP5DETR four-di git lot number is represented by xxxx. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13530-0-9/16(0)

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